A natural way to address the scalability of quantum devices is to design and realise arrays of individual quantum objects with nearest-neighbor interaction. In large-scale semiconductor quantum processors, a quantum bit is encoded in the spin of an isolated electron, trapped in an array of quantum dots (QDs) [1]. Over the years, we have studied devices with an increasing number of QDs, in designs that allow for the coherent control of individual spin [2]. To scale up spin qubit devices to computationally useful size, it is necessary to achieve very large-scale standards for quantum dot integration and control. Therefore, demonstrating the extensive and scalable characterization and calibration of QD systems is crucial for the development of our quantum processor. Recently, CEA-Leti has acquired a unique automatised measurement tool for 300-mm wafers at cryogenic temperature, which gives us a new way to develop intelligent and efficient characterization techniques (Figure 1).
Objectives  The systematic characterization of the QD control parameters scales with the number of controls and QDs. The dense exploration of the parameter space limits the experimental throughput of relevant data points. To evaluate the quality and the functionality of the silicon quantum dots, elaborated chains of device characterizations are employed. The candidate will develop and implement a characterization protocol for the charge stability and electric noise of quantum devices. It will allow both identifying the instability sources, and giving feedback to the process integration team. It will also enable the device selection for further investigations. There, the candidate will develop a protocol/algorithm to prepare and evaluate the quantum device metrics. The systematic evaluation of these metrics at the wafer scale will give a statistical insight on semiconductor quantum devices. The precise understanding of the QD metrics will permit to implement large-scale functional tests for the quantum devices, and to explore more complex device geometries. For this, the candidate will have the opportunity to use the low-noise and low-temperature (2K) electrical measurement setup for 300-mm wafers available at CEA. The development of qubit models (circuit engineering type) and automation of the procedures required for the data generation and analysis are also envisioned in this work.
Collaborations: This work is part of a large collaborative effort to develop and push the technology of spin qubit in silicon and investigate its potential scalability. Therefore, the candidate will work in close collaboration with the LETI’s integration team designing the quantum devices, and with the Institut Néel and CEA-IRIG where the quantum devices are characterized at mK temperatures and used as qubit platforms.
[1] Vinet, M. et al. Towards scalable silicon quantum computing, IEDM (2018).
2] Mortemousque, P.-A. et al. Nat. Nanotechnol. (2020) doi:10.1038/s41565-020-00816-w

We are looking for a motivated candidate, with an interest for experimental physics. This position requires skills in semiconductor physics. A strong interest in algorithm programming, quantum physics and machine learning is required. A knowledge of low-temperature physics and/or nano-fabrication techniques will be appreciated but is not mandatory.