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Evaluation & enhancements of the parallel single path paradigm for real-time applications H/F


Vacancy details

General information

Organisation

The French Alternative Energies and Atomic Energy Commission (CEA) is a key player in research, development and innovation in four main areas :
• defence and security,
• nuclear energy (fission and fusion),
• technological research for industry,
• fundamental research in the physical sciences and life sciences.

Drawing on its widely acknowledged expertise, and thanks to its 16000 technicians, engineers, researchers and staff, the CEA actively participates in collaborative projects with a large number of academic and industrial partners.

The CEA is established in ten centers spread throughout France
  

Reference

2021-19343  

Description de l'unité

One of three institutes that comprise CEA Tech, the List institute is committed to technological innovation in digital systems. Within the DSCIN department, the LECA laboratory invests efforts in three main fields:

- Analysis and verification of timing properties of embedded systems

- Electronic Design Automation (EDA)

- Hardware design for Artificial Intelligence (AI) applications


http://www-list.cea.fr/

Position description

Category

Engineering science

Contract

Internship

Job title

Evaluation & enhancements of the parallel single path paradigm for real-time applications H/F

Subject

The focus of this internship is:

1) to evaluate in details a hardware prototype of the parallel single path paradigm over a set of WCET benchmarks, such as the one from the Mälardalen or the MiBench benchmarks and

2) identify possible optimizations by analyzing the obtained results, then implement and evaluate them.

First, the PSP hardware extension must be fully ported to the Leros processor that comes with the PSP LLVM back-end pass and thus enables the compilation of C input programs with the appropriate ISA extensions for PSP. Then, benchmarking can be performed and obtained results will be compared against the classical single-path paradigm. Amongst possible optimizations for PSP, taking advantage of live registers provided by LLVM will be investigated.

Contract duration (months)

6 months

Job description

Safety-critical systems such as autonomous vehicles and modern avionic computers have to satisfy strong timing requirements. A failure to meet a timing constraint, missing a deadline for example, may result in serious outcomes like loss of life. Therefore, it is crucial to compute safe timing bounds for these systems.

 

To do so, the worst-case execution time (WCET) of each task involved in a safety-critical system must be estimated before being used in a schedulability analysis. The tightness of these WCET estimations is a key issue for ensuring that the required processing power is not over-estimated and thus does not lead to unnecessary increase in the cost of real-time systems. When using static analyses for performing WCET analysis [1], WCET over-estimations come from abstractions in both the hardware and program models used. The code generation technique called « single-path » [2] reduces the number of paths that needs to be considered in a WCET analysis, simplifying program modeling and thus increasing the temporal predictability. However, using this approach, the WCET increases as paths within programs are sequentially executed. The parallel single-path (PSP) paradigm reduces this overhead by executing, in parallel and over several cores, branches of input programs due to conditional statements. A first prototype of this PSP paradigm was developed as an hardware and software extension to the family of Lipsi/Leros processors [3,4] (designed using the Chisel3 hardware construction language [5]) and their associated LLVM compilation tool chain. 

 

The focus of this internship is 1) to evaluate in details this prototype over a set of WCET benchmarks, such as the one from the Mälardalen [6] or the MiBench benchmarks and 2) identify possible optimizations by analyzing the obtained results, then implement and evaluate them. First, the PSP hardware extension must be fully ported to the Leros processor that comes with the PSP LLVM back-end pass and thus enables the compilation of C input programs with the appropriate ISA extensions for PSP. Then, benchmarking can be performed and obtained results will be compared against the classical single-path paradigm. Amongst possible optimizations for PSP, taking advantage of live registers provided by LLVM will be investigated. This subject will thus expand your skills in the co-design of systems: both hardware design at the processor level and back-end compilation steps, i.e. in generating appropriate assembly code for a given processor.

Applicant Profile

Computer engineering student (final year) or master2 student

  • Background in design of computer architecture (VHDL, Verilog, Chisel, etc.)
  • Background in compilation techniques (LLVM, gcc)

Position location

Site

Saclay

Job location

France, Ile-de-France, Essonne (91)

Location

  Palaiseau