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Implementation and validation of a hardware countermeasure against physical attacks in a RISC-V core H/F

Vacancy details

General information


The French Alternative Energies and Atomic Energy Commission (CEA) is a key player in research, development and innovation in four main areas :
• defence and security,
• nuclear energy (fission and fusion),
• technological research for industry,
• fundamental research in the physical sciences and life sciences.

Drawing on its widely acknowledged expertise, and thanks to its 16000 technicians, engineers, researchers and staff, the CEA actively participates in collaborative projects with a large number of academic and industrial partners.

The CEA is established in ten centers spread throughout France



Description de l'unité

Located in Grenoble, Leti is a CEA research institute which works daily to create the link between research in micro and nanotechnologies and industrial or general public applications with the aim of improving everyone's quality of life.

Leti has more than 2,000 high-level researchers and has offices in the US and Japan.

Position description





Job title

Implementation and validation of a hardware countermeasure against physical attacks in a RISC-V core H/F


RISC-V is an open instruction set architecture (ISA). It offers an alternative to proprietary solutions and benefits from a very dynamic ecosystem. Several implementations on FPGA and silicon have been made. In this case, The OpenHW Group, a European consortium, offers a whole family of 32-bit and 64-bit RISC-V cores.

Contract duration (months)


Job description

 The CEA addresses the subject of processor security against physical vulnerabilities by working on these open source architectures to implement hardware countermeasures. Several CEA teams are working on the design of an ASIC on 18 nm FDSOI technology. The latter will embed several RISC-V cores and different IPs including a 64-bit secure core based on the OpenHW CVA6.


The subject of the internship is to implement and validate a countermeasure against fault injection attacks, already specified, in the CVA6 core emulated on FPGA. In addition, the trainee will also participate in verifying and validating the secure core.

Methods / Means

Linux / C / Python

Applicant Profile

The candidate must have good skills in hardware design (Verilog or VHDL) and some basics in processor architecture. A genuine enthusiasm for scientific research and the ability to communicate in a pluridisciplinary environment will be highly valued.

Position location



Job location

France, Auvergne-Rhône-Alpes, Isère (38)



Candidate criteria


  • French (Fluent)
  • English (Fluent)

Prepared diploma

Bac+5 - Master 2

PhD opportunity



Position start date