Testing is a fundamental phase of design and production of integrated circuits. It ensures not only the quality of electronic chips, but also compliance with security constraints required by several applications. Memory Built-In Self-Test (MBIST) and Logic Built-in Self-Test (LBIST) are widely used techniques for testing circuit memories and logic. It entails integrating extra hardware components around the memory, which are capable of efficiently performing testing operations. On the other hand, Near Memory Computing (NMC) is emerging as a promising solution to accelerate processing and to reduce energy consumption in integrated circuits. To study these architectures, the CEA has developed the Computational-SRAM (C-SRAM). Controlled by a processor, this SRAM memory is surrounded by logic that enables it to perform efficient computations directly near the memory. Current application domains include Artificial Intelligence (AI) and cryptography, particularly post-quantum cryptography (PQC). In this context, the CEA is exploring the testability of memories integrated into NMC systems, leveraging the existing computing capabilities in such architectures. In this intern, the aim is to evaluate the fault coverage of the C-SRAM and to propose a solution to increase it while limiting the hardware modifications.

This internship is intended for master (or engineering school) students in their last year. It is possible to base the master’s thesis on the subjects treated during the internship.
The student will have a 6-month remunerated stage contract, plus benefits for accommodation in Grenoble and public transportation.