General information
Organisation
The French Alternative Energies and Atomic Energy Commission (CEA) is a key player in research, development and innovation in four main areas :
• defence and security,
• nuclear energy (fission and fusion),
• technological research for industry,
• fundamental research in the physical sciences and life sciences.
Drawing on its widely acknowledged expertise, and thanks to its 16000 technicians, engineers, researchers and staff, the CEA actively participates in collaborative projects with a large number of academic and industrial partners.
The CEA is established in ten centers spread throughout France
Reference
2026-42076
Description de l'unité
This internship will take place at the CEA List institute, located at the CEA Grenoble premises, within the LIIM laboratory (Laboratory for Integrated Multi-sensor Intelligence). This laboratory focuses on developing algorithms for Embedded Artificial Intelligence, data fusion, and environmental perception deployed in cyber-physical systems. The laboratory designs hardware and software demonstration platforms that utilize these algorithms combined with innovative technologies often integrated into integrated circuits.
CEA-List is one of the research institute of CEA's technological research division. Dedicated to intelligent digital systems, its mission is to carry out cutting-edge technological developments on behalf of industrial partners to create value.
Position description
Category
Electronics components and equipments
Contract
Internship
Job title
Internship - Digital circuit design for artificial intelligence - M/F
Subject
Integration of a matrix multiplication accelerator for artificial intelligence algorithms in a near-sensor embedded computing circuit architecture
Contract duration (months)
5 to 6 months
Job description
Context:
As part of our ASIC design activities, we are developing an embedded computing platform based on a RISC-V processor. For near-sensor data processing, we use transformer-based artificial intelligence (AI) algorithms. These models significantly improve performance but require high computational power.
To increase the platform's computing capacity while adhering to a strict power budget, integrating optimized hardware accelerators can be a solution, particularly for matrix-vector and matrix-matrix multiplication operations.
Additionally, due to limited memory, it is necessary to compress AI models, for example by storing network weights in low-bit binary formats (less than one byte), which is below the granularity of a general-purpose processor. Hardware accelerators must therefore support these representations.
Internship objective:
The main objective of the internship is to integrate a reduced-precision matrix multiplication accelerator into the RTL (SystemVerilog) platform. In addition to hardware design, the internship will include demonstrating the software environment that enables controlling computations on the accelerator from the embedded processor. Based on an existing design, the accelerator can be optimized to support new binary formats, such as 4-bit floating-point (FP4).
Work plan:
- v Mastering the hardware architecture of the platform and the simulation environment (RTL level)
- v Study of the compute accelerator and integration solutions within the platform
- v Integration of the accelerator, implementation of the software flow for deploying computations on the accelerator, and functional validation
- v Silicon projection (performance, power consumption, area) using a logic synthesis flow
- v Performance estimation, energy efficiency assessment for target applications
- v Evolution of the accelerator design to integrate new binary formats and revisiting previous steps
Methods / Means
EDA tools
Applicant Profile
- End of Master (Bac+5) or engineering school
- Skills in embedded systems architecture, digital systems design, RTL design, embedded software
- Proficiency in VHDL, SystemVerilog, C/C++, Python
- Knowledge of artificial intelligence, neural networks could be useful
Position location
Site
Grenoble
Job location
France, Auvergne-Rhône-Alpes, Isère (38)
Location
Grenoble
Candidate criteria
Languages
English (Intermediate)
Prepared diploma
Bac+5 - Diplôme École d'ingénieurs
Recommended training
Master / Engineering degree
PhD opportunity
Non
Requester
Position start date
01/02/2027
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