Informations générales
Entité de rattachement
Le CEA est un acteur majeur de la recherche, au service des citoyens, de l'économie et de l'Etat.
Il apporte des solutions concrètes à leurs besoins dans quatre domaines principaux : transition énergétique, transition numérique, technologies pour la médecine du futur, défense et sécurité sur un socle de recherche fondamentale. Le CEA s'engage depuis plus de 75 ans au service de la souveraineté scientifique, technologique et industrielle de la France et de l'Europe pour un présent et un avenir mieux maîtrisés et plus sûrs.
Implanté au cœur des territoires équipés de très grandes infrastructures de recherche, le CEA dispose d'un large éventail de partenaires académiques et industriels en France, en Europe et à l'international.
Les 20 000 collaboratrices et collaborateurs du CEA partagent trois valeurs fondamentales :
• La conscience des responsabilités
• La coopération
• La curiosité
Référence
2026-42461
Description de l'unité
The Laboratory for Innovative Functions for Mixed-Signal Circuits (LFIM) is tasked with the study and design of digital and mixed-signal electronic circuits that meet requirements for energy efficiency, compact size, real-time operation, and operational reliability.
These circuits are applied in a wide range of systems and fields, such as high-performance computing architectures and low-power embedded systems—areas that now converge in the context of quantum computing, where a cryogenic environment imposes conflicting demands regarding performance and power dissipation.
The technologies developed within the laboratory leverage the latest advancements in nanoelectronics. The LFIM studies, designs, and integrates digital and mixed-signal processing architectures onto silicon to address application needs in areas including high-performance computing, the Internet of Things (IoT), radio-frequency (RF) circuits, and cyber-physical systems.
Description du poste
Domaine
Technologies micro et nano
Contrat
Stage
Intitulé de l'offre
Internship Hybrid DRAM: Next-Gen ferroelectric memory for energy-constrained systems-Grenoble-H/F
Sujet de stage
The objective of this internship is to investigate and design the critical circuit building blocks of a hybrid DRAM. This memory supports two storage modes: volatile and persistent. This dual functionality is enabled by ferroelectric technology, which allows information to be stored either as remanent polarization for non-volatile operation or as electrical charge for volatile operation. The results will guide the development of next-generation hybrid memory architectures for applications with stringent energy constraints.
Durée du contrat (en mois)
6 mois
Description de l'offre
As an intern at the CEA, you will have the opportunity to work within a world-renowned research environment. Our teams consist of passionate and dedicated experts, providing an ideal setting for learning and collaboration. You will have access to state-of-the-art equipment and top-tier research resources to carry out your assignments. The work conducted may potentially lead to a scientific publication.
Context :
Hafnium–zirconium oxide (HZO) ferroelectric stacks enable the development of highly scalable memories compatible with CMOS fabrication processes. These technologies offer the potential for integration densities comparable to those of DRAM, while supporting both volatile and non-volatile operating modes.
What do we expect from you?
The objective of this internship is to assess the potential of these hybrid memories for energy-constrained systems through the design and evaluation of critical circuit blocks. This work will contribute to establishing a design basis for future hybrid memory architectures.
During the internship, the student will design circuits of key building blocks of a memory subarray, such as sense amplifiers and replica timing paths, using industry-standard circuit design and simulation tools. The resulting circuits will be evaluated in terms of timing performance, power and energy consumption, and operating stability.
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Moyens / Méthodes / Logiciels
Outils de conception et de simulation électrique (Spice)
Profil du candidat
Desired skills and experience
This internship is intended for students in the final year of a Master’s degree or engineering programme, preferably with a background in electronics, microelectronics, or embedded systems.
Solid circuit design skills, particularly in schematic capture and SPICE simulation and language, are desirable, together with a good understanding of memory hierarchies and low-power design principles.
The internship can form the basis of a PhD’s thesis. A funded PhD position will subsequently be available, offering an opportunity to continue this research.
Localisation du poste
Site
Grenoble
Localisation du poste
France, Auvergne-Rhône-Alpes, Isère (38)
Ville
Grenoble
Critères candidat
Langues
- Anglais (Intermédiaire)
- Français (Courant)
Diplôme préparé
Bac+5 - Diplôme École d'ingénieurs
Formation recommandée
Master 2 / Ecole d'ingénieurs
Possibilité de poursuite en thèse
Oui
Demandeur
Disponibilité du poste
01/02/2027
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