Once a chip design is finished, after the Place & Route and layout, it is possible to analyze each gate location and back-annotate the ideal circuit netlist with an additional delay information. Then, very advanced tools like Synopsys PrimeTime can be run to perform time closure or to have the power consumption prediction for the different chip domains. Based on these outputs, designers will be able to
co-optimize the design with respect to the expected system requirements in terms of Power, Performance and Area (PPA). System Technology Co-Optimization (STCO) is an approach that handles a wide range of technological and design possibilities to target the expected PPA figures. It addresses overall system optimization across different abstraction levels/hierarchies, and needs to comprehend not only integration technology, circuits, architectures and software but also their interactions with the power delivery, cooling and system costs.

The proposed internship will participate to the development of an STCO methodology with a focus on various technological aspects. The primary objective is to conduct Design Space Exploration (DSE) by simulating, at system-level, different configurations through changes in the system architecture, the used memory technology or the application, in order to identify the optimal design. The intern will use a virtual prototyping platform based on SystemC[1] simulation engine where the IPs are modeled using the TLM standard[2]. In the development of these systemC/TLM models, power estimation is crucial for optimizing design efficiency and performance. Power estimation techniques rely on the dependence of simulation’s input data and their profiling methodologies. Depending on the desired simulation cost and accuracy trade-off, we can:

• Use detailed runtime information gathered from back-annotation flows from real layouts.
• Use analytical models to predict power consumption based on established equations and assumptions, once preliminary data are available from datasheets, literature or from existing chip designs.

The intern will contribute in developing and validating power estimation methodologies for different SoC IPs. The role involves performing RTL-level and back-annotated gate-level simulations and extracting switching activity (VCD/FSDB) for detailed power analysis in Synopsys PrimePower under various workloads and correlate simulation results with datasheet or literature data to verify and improve modeling accuracy.

[1] D. A. S. Committee, “IEEE standard for standard SystemC language reference manual,” IEEE Std 1666-2023.

[2] T. O. S. I. (OSCI), “OSCI TLM-2.0 language reference manual,” 2009.

This offer is dedicated to master students looking for an ambitious research-oriented internship, using the state-of-the-art standard tools offered by the main Electronic Design Automation CAD vendors. If you are looking for an experience in system modelling and low- or high-level simulation of integrated circuit with industrial-grade tools and processes, this internship is perfect for you! It is required to have graduate-level experience in system architecture and be familiar with some across Hardware Description Language and/or SystemC modelling and/or software development (C/C++ and python). Knowledge of the ASIC design flow is a plus and will be reinforced during the internship.

This internship is intended for master (or engineering school) students in their last year. It is possible to base the master’s thesis on the subjects treated during the internship.
This internship is in close collaboration with a 3rd year PhD student.
This internship can open opportunities for later PhD position in the team or the department.
The student will have a 6-month remunerated stage contract, plus benefits for accommodation in Grenoble and public transportation.