Within the advanced transistors laboratory  (LTA) and in close collaboration with the silicon imaging laboratory (LIS), join CEA-LETI to develop the applications of tomorrow. This position is part of the sequential 3D integration developed within the FAMES project (https://fames-pilot-line.eu/3d-options-for-enhanced-integration). It aims to innovate on future architectures and more specifically on disruptive pixel design.

We are looking for an analog designer with a strong understanding of transistor-level design, capable of collaborating closely with our technology integration experts to design new generations of innovative pixels: miniaturization, new functionalities, advanced readout modes, etc.

Based on our disruptive technologies (sequential 3D integration, 3D MIM capacitors, etc.), and from the challenges identified during the work, the candidate will be led to propose new integration approaches and evaluate their technological feasibility.

Main missions :

- Reflect on integration and relevant technological dimensions in collaboration with the LTA technology engineers, using process modeling tools (e.g., Coventor) for a variety of applications. (30%)

- Design pixels and identify technological challenges related to the miniaturization of 3D pixels and propose innovative solutions. (60%)

- Conduct TCAD studies and simulations to validate the functionalities of the proposed designs. (10%)

Depending on your interests, it will be possible (and encouraged) to enhance your work through scientific publications or patent filings. There is also a potential opportunity to lead cross-functional tasks evaluating analog design with other CEA application laboratories related to sequential 3D integration.

This fixed-term contract is ideal if you wish to consolidate or leverage your skills in pixel design or semiconductor physics within a stimulating research environment.

Desired Profile:

- Master's degree or PhD in the field of transistor-level analog design and/or semiconductor physics.

- Ability to work within a multidisciplinary team (design, TCAD simulation, technology integration).

Additional assets:

- Experience in CMOS imaging and ideally in pixel design.

- Knowledge of cleanroom integration and device integration flow (photodiode, transistor, etc.).

Software used:

-Virtuoso/Cadence.

- Synopsys TCAD.

- Coventor or equivalent process emulation software.