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CMOS/spintronics co-design of a coupling chip for Ising Machines based on STNOs networks

Vacancy details

General information


The French Alternative Energies and Atomic Energy Commission (CEA) is a key player in research, development and innovation in four main areas :
• defence and security,
• nuclear energy (fission and fusion),
• technological research for industry,
• fundamental research in the physical sciences and life sciences.

Drawing on its widely acknowledged expertise, and thanks to its 16000 technicians, engineers, researchers and staff, the CEA actively participates in collaborative projects with a large number of academic and industrial partners.

The CEA is established in ten centers spread throughout France



Position description


Electronics components and equipments



Job title

CMOS/spintronics co-design of a coupling chip for Ising Machines based on STNOs networks


The post doc project is a contribution to the design of Ising machines which are computing architectures inspired from biology and physics able to solve complex optimization problems. Under the scope of SpinIM project (french ANR funding), the applicant will contribute to the demonstration of an Ising machine based on the electrical coupling of spin torque nano-oscillators (STNO). The post doc will design the configurable CMOS chip implementing the electrical coupling. He will propose a VerilogA model of the STNO with the help of Spintec experience on STNO theory. The post doc will optimize the design of the CMOS chip from schematics to layout and will assess its performances in laboratory. Finally, the post doc will participate to the full demonstration of the Ising machine consisting in the CMOS chip with the STNO network on optimization tasks. The post doc will take place in LGECA laboratory of CEA-Leti which have gained experience on the co-design of CMOS-Spintronics circuits.

Contract duration (months)

1 year + possible extension of 1 year

Job description

The post doc will take place in LGECA laboratory of CEA-LETI (design of analog and mixed integrated circuits) and in collaboration with SPINTEC teams (physics of STNOs).

The main objective of the post doc is to contribute to the demonstration of the design of an Ising Machine based on networks of STNOs by designing a fully integrated CMOS circuit ensuring the coupling of the STNOS. The designed chip should allow the programmability of the network in terms of number of connections and their respective weights. The scientific path towards this goal is the classical path for the design of heterogeneous systems: architecture study, circuit design followed by its fabrication and at last, fully assessment of the prototype performances with and without the STNO network.

The goal of the architecture study is to determine the necessary building blocks for the coupling chip and their main specifications. Another task will be the writing of an electrical model of the STNO that should permit the co-simulation of the CMOS chip with the STNO network using standard electrical simulators (spectre, eldo, hspice…). This will allow the verification of the compliance of the CMOS chip with the STNO network during the CMOS chip design phase. For that purpose, and based on physics equations developed by SPINTEC, the post doc will have to write a verilogA or VHDL-A model that will accurately reproduce the STNO behaviour in both time and frequency domains.

The design phase of the CMOS coupling chip will consist in the proposition of the most adequate schematics of the different building blocks and in their assembly. The post doc will optimize the design by minimizing the overall noise,  power consumption and  parasitics. He will have to optimize the layout and proceed to the classical verifications before fabrication of the chip. The post doc will beneficiate of the experience of LGECA laboratory in the field of the design of analog integrated circuits.

The test and validation phase will be a two-time process. In a first step, and during the fabrication of the chip, the post doc will propose the test plan that will ensure the full assessment of the electrical performances of the coupling chip in a stand-alone mode and he will design and optimize the PCB. The post doc will fully assess the electrical performances of the chip using the test environment provided by the LMTE laboratory of the CEA Leti. In a second step, the post doc will have to actively participate to the test and demonstration of the full Ising Machine composed of the coupling chip and the STNO network.

The post doc applicant should provide a particular attention to patenting and publishing research results.



Methods / Means

VerilogA - Cadence IC design tools - Lab Electrical characterization

Applicant Profile

The applicant should have a PhD in electronics with a specialization in the design of analog/RF integrated circuits. Ideally, the candidate should be familiar with semiconductor physics. Mastering a modelling language as VerilogA or VerilogAMS as well as PCB design software will be appreciated. Curiosity, problem solving spirit, autonomy and good communication skills are required.

Position location



Job location

France, Auvergne-Rhône-Alpes, Isère (38)



Candidate criteria


English (Fluent)

Prepared diploma

Bac+8 - Doctor of philosophy (PhD)

Recommended training

Electronics - Integrated Circuit Design


Position start date